VLSI Design and Technology MCQ PDF for online exam.
1] Long form of VHDL
A. Very High speed Horizontal Description Language
B. Very High Super Hardware Description Language
C. Very High Speed Hardware Description Language
D. Very Large Scale High spread Hardware Description language
ANSWER:c
2] which is data object
A. std_logic
B. constant
C. boolean
D. INTEGER
ANSWER:B
3] In process all statements are ________________execute.
A. parallel
B. random
C. sequential
D. concurrent
ANSWER:C
4] which statement is true
A. procedure return many values
B. package store in STD_LOGIC library
C. function return maximum values
D. case statement use in structural modeling
ANSWER:A
5] mealy machine means
A. output depends on present state only
B. output depends on clock signal only
C. output depends on input as well as present state
D. none of above
ANSWER:C
6] which statement is nonsynthesizable
A. assert statement
B. std_logic_vector data type
C. case statement
D. with select statement
ANSWER:A
7] variable declare
A. In entity
B. in process
C. after architecture program
D. none of above
ANSWER:B
8] _______is data type in vhdl
A. signal
B. variable
C. array
D. file
ANSWER:C
9 ]________________is nonsynthesizable statement
A. interger data type in entity
B. for loop statement in vhdlC. structural modeling style in VHDL
D. variable data object in VHDL
ANSWER:A
10 ] Which is encoding technique of FSM
A. moore
B. mealy
C. one hot
D. excess-code
ANSWER:C
11] Which among the following is pre-defined in the standard package as one-dimensional array type
comprising each element of BIT type
A. Bit type
B. Bit_vector type
C. Boolean type
D. All of the above
ANS:B
Which data type in VHDL is non synthesizable & allows the designer to model the objects of dynamic
nature?
A. Scalar
B. Access
C. Composite
D. File
ANS:B
In VHDL, which object/s is/are used to connect entities together for the model formation
A. Constant
B. VariableC. Signal
D. All of the above
ANS:C
In Net-list language, the net-list is generated _______synthesizing VHDL code.
A. Before
B. At the time of (during)
C. After
D. None of the above
ANS:C
Among the VHDL features, which language statements are executed at the same time in parallel flow
A. Concurrent
B. Sequential
C. Net-list
D. Test-bench
ANS:A
In a VHDL program, the architecture can have more than one entity.
A. True
B. False
ANS:B
Which of the following describes the structure of a VHDL code correctly
A. Library Declaration; Configuration; Entity Declaration; Architecture Declaration
B. Library Declaration; Entity Declaration; Configuration; Architecture Declaration
C. Library Declaration; Configuration; Architecture Declaration; Entity Declaration
D. Library Declaration; Entity Declaration; Architecture Declaration; Configurations
ANS:D
Multiple processes in a VHDL code are executed ______.A. Sequentially
B. Concurrently
C. Based on the order of elements in the sensitivity list
ANS:B
_______ is the process of converting design information to a set of logic equations using EDA tools.
A. Simulation
B. Optimization
C. Synthesis
D. Verification
ANS:C
The statements inside a VHDL process are __________.
A. Primitive
B. Sequential
C. Concurrent
D. Sequential or concurrent
ANS:B
Which among the following is/are regarded as the function/s of translation step in synthesis process
A. Conversion of RTL description to boolean unoptimized description
B. Conversion of an unoptimized to optimized boolean description
C. Conversion of unoptimized boolean description to PLA format
D. All of the above
ANS:A
How much logics contents in std_logic data type
A. 2
B. 9C. 8
D. 16
ANS:B
Which data type is non synthesizable
A. std_logic
B. std_logic_vector
C. integer
D. bit
ANS:C
How much input bit content of std_logic_vector(5 downto 0)
A. 5
B. 2
C. 6
D. 4
ANS:C
What is std_logic_1164 in vhdl programing
A. Package
B. Data type
C. Data object
D. synthesizer
ANS:A
How much input bit content of std_logic_vector(5 downto 0)
A. 5
B. 2
C. 6
D. 4
ANSWER:Cs
et-1 17) Which of the following is true about packages?
a) Package is collection of libraries
b) Library is collection of packages
c) Package is collection of entities
d) Entity is collection of packages
ANS:B
set-2 18) It is possible to modify the STD_LOGIC_1164 package of IEEE library.
a) True
b) False
ANS:B
set-3 19) Which of the following is the correct use of the signal?
a) To set a default value
b) To pass value between circuits
c) To declare a variable
d) To represent local information
ans:b
20) What is the use of a variable?
a) To represent local value
b) To represent default value
c) To set default valued) To declare a subprogram
ans:a
21) Use of constants is to _________
a) Represent wires
b) Represent local information
c) Represent default value
d) Pass value between entities
ans:c
23) For any concurrent assignment statement, which of the following is true?
a) The statement is executed once
b) The statement is executed twice
c) The value of left operand is assigned to right operand
d) The statement is executed as many times as the value changes
ANS:D
2 set-1 24) Which of the following is the correct architecture for a simple Nand gate?
A) ARCHITECTURE my_arch OF nand_gate IS
BEGIN
x <= a NAND b;
END my_arch;
B)ARCHITECTURE my_arch OF nand_gate IS
x <= a NAND b;
END behavioral;
C)BEGIN
ARCHITECTURE behavioral OF nand_gate IS
x <= a NAND b;
END my_arch;D)ARCHITECTURE nand OF nand_gate IS
BEGIN
x <= a NAND b;
END nand_gate;
ANS:A
2 set-2 25) In the following statements, y and z are equivalent to________
y <= NOT a AND b;
z <= NOT (a AND b);
a) y <= a’+b’ and z <= (a.b)’
b) y <= (a+b)’ and z <= a’+b’
c) y <= a’b and z <= a’+b’
d) y <= a+b’ and z <= a.b
ANS:C
2 set-3 26) Which of the following is correct syntax for component declaration?
a)
COMPONENT component_name IS
PORT ( port_mode : type port_name;
port_mode : type port_name;
….);
END component_name;
b)
COMPONENT component_name IS
PORT ( port_mode : type port_name;
port_mode : type port_name;
….); END COMPONENT;
c)
COMPONENT component_name IS
PORT ( port_name : mode type;
port_name : mode type;
….);
END component_name;
d)
COMPONENT component_name IS
PORT ( port_name : mode type;
port_name : mode type;
….);
END COMPONENT;
ans:D
2 set-1 28) Which of the following represents the correct order for keywords?
a) IF, THEN, ELSIF, THEN, ELSE
b) IF, ELSE, THEN, ELSIF, THEN
c) IF, ELSIF, THEN, ELSE, THEN
d) IF, THEN, ELSE, THEN, ELSIF
ANS:A
2 set-2 29) Which of the following keyword is not associated with IF statement?
a) ELSEb) THEN
c) ELSIF
d) WHEN
ANS:D
2 set-3 30) In case any of the conditions is not covered by ‘cases’ in the case statement, which of the
following keyword can be used to cover all those conditions?
a) ELSE
b) ELSIF
c) REMAINING
d) OTHERS
ANS:D
2 set-1 31) A for loop is initiated as given below, in total how many iterations will be there for the
FOR loop?
FOR i IN 0 TO 5 LOOP
a) 3
b) 4
c) 5
d) 6
ANS:D
2 set-2 22) How to declare a constant in VHDL?
a) CONSTANT name : type := value;
b) CONSTANT name := value;
c) CONSTANT name := type := value;
d) CONSTANT name := type : value;
ans:a2 set-2 32) What will be the value of x in the following code?
SIGNAL x : IN UNSIGNED (3 DOWNTO 0 );
x <= “1101”;
a) 5
b) 13
c) -5
d) 12
ANS:B
2 set-3 33) If a and b are two STD_LOGIC_VECTOR input signals, then legal assignment for a and b
is?
a) x <= a.b
b) x <= a OR b
c) x <= a + b
d) x <= a && b
ANS:B
2 set-1 27) Which of the following signal cause the process to execute?
PROCESS (clr)
BEGIN
IF (clr = ‘1’) THEN
y <= ‘0’;
ELSE
y <= input;
END PROCESS;
a) inputb) y
c) clr
d) x
ans:c
2 set-2 34) Refer to the VHDL code given below, how many input-output pins are there in AAA
entity?
ENTITY AAA IS
Port ( a,b : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END AAA;
a) 5
b) 4
c) 3
d) 2
ANS:C
2 set-3 35) Which of the following is an entity declared for a full adder?
a)
ENTITY full_adder IS
PORT(a, b, c : IN BIT;
s, co : OUT BIT);
END full_adder;
b)ENTITY full_adder IS
PORT (a ,b : IN BIT;
s, c : OUT BIT);
END full_adder;
c)
ENTITY full_adder
PORT(a, b, c : IN BIT;
s, co : OUT BIT);
END full_adder;
d)
ENTITY full_adder IS
PORT (a, b, c, s, co : BIT);
END full_adder;
ans:a
Procedures are useful when _________
a) Functions are not synthesizable
b) Signals are needed to be declare
c) Multiple values are needed as a result
d) Architecture can’t contain some statementans:c
Procedure doesn’t have a return type.
a) True
b) False
ans:a
A procedure can’t contain a _______ statement.
a) WAIT
b) IF
c) RETURN
d) CASE
ans:c
. A function is a ________ code.
a) Concurrent
b) Sequential
c) Concurrent as well as sequential
d) Process oriented
ANS:B
How many return arguments can be there in the function?
a) 1
b) 2
c) 3
d) 4
ANS:A
A function call can be a concurrent as well as a sequential statement.
a) True
b) False
ANS;A
In VHDL, which object/s is/are used to connect entities together for the model formation?
a. Constant
b. Variable
c. Signal
d. All of the above
ANS:C
Hold time is defined as the time required for the data to ________ after the triggering edge of clock.
a. Increase
b. Decrease
c. Remain stable
d. All of the above
ANS:C
Which of the following is true about packages?
a) Package is collection of libraries
b) Library is collection of packages
c) Package is collection of entities
d) Entity is collection of packages
ANS:B
A package may consist of _________ design units.
a) 2
b) 3
c) 4
d) 5
ANS:A
Any item declared in a package declaration section are visible to _______
a) Every design unit
b) Package body only
c) Library containing that package
d) Design unit that USE the package
ANS:D
If a user wants to include his/her own package in the body, which library he/she must use?
a) STD
b) IEEE
c) WORK
d) STD_LOGIC
ANS:C
It is possible to modify the STD_LOGIC_1164 package of IEEE library.
a) True
b) False
ANS:B
Which of the following is the correct use of the signal?
a) To set a default value
b) To pass value between circuits
c) To declare a variable
d) To represent local information
ans:b
What is the use of a variable?a) To represent local value
b) To represent default value
c) To set default value
d) To declare a subprogram
ans:a
Use of constants is to _________
a) Represent wires
b) Represent local information
c) Represent default value
d) Pass value between entities
ans:c
How to declare a constant in VHDL?
a) CONSTANT name : type := value;
b) CONSTANT name := value;
c) CONSTANT name := type := value;
d) CONSTANT name := type : value;
ans:a
Which of the following can’t be declared in an architecture?
a) Signal
b) Constant
c) Variable
d) BIT_VECTOR
ans:c
Set 1
clock jitter means A. variation in clock signal
B. variation in fan out
C. variation in power dissipation
D. variation in supply voltage
ANSWER:A
et-1 1) which statement is nonsynthesizable
A. assert statement
B. std_logic_vector data type
C. case statement
D. with select statement
ANSWER:A
set-2 2) ________________is nonsynthesizable statement
A. interger data type in entity
B. for loop statement in vhdl
C. structural modeling style in VHDL
D. variable data object in VHDL
ANSWER:A
set-3 3) Which is encoding technique of FSM
A. moore
B. mealy
C. one hot
D. excess-code
ANSWER:C
set-1 4) In Net-list language, the net-list is generated _______synthesizing VHDL code.
A. Before
B. At the time of (during)
C. AfterD. None of the above
ANS:C
set-2 5) Among the VHDL features, which language statements are executed at the same time in
parallel flow
A. Concurrent
B. Sequential
C. Net-list
D. Test-bench
ANS:A
set-3 6)_______ is the process of converting design information to a set of logic equations using
EDA tools.
A. Simulation
B. Optimization
C. Synthesis
D. Verification
ANS:C
set-1 8) Which among the following is an output generated by synthesis process
A. Attributes & Library
B. RTL VHDL description
C. Circuit constraints
D. Gate-level net list
ANS:D
set-2 9) Which among the following is/are regarded as the function/s of translation step in synthesis
process
A. Conversion of RTL description to boolean unoptimized description
B. Conversion of an unoptimized to optimized boolean descriptionC. Conversion of unoptimized boolean description to PLA format
D. All of the above
ANS:A
set-3 10) Which data type is non synthesizable
A. std_logic
B. std_logic_vector
C. integer
D. bit
ANS:C
set-1 11) Procedures are useful when _________
a) Functions are not synthesizable
b) Signals are needed to be declare
c) Multiple values are needed as a result
d) Architecture can’t contain some statement
ans:c
set-2 12) Procedure doesn’t have a return type.
a) True
b) False
ans:a
set-3 13) A procedure can’t contain a _______ statement.
a) WAIT
b) IF
c) RETURN
d) CASE
ans:c
2 SET-1 14) A function is a ________ code.
a) Concurrent
b) Sequential
c) Concurrent as well as sequential
d) Process oriented
ANS:B
set-1 15) How many return arguments can be there in the function?
a) 1
b) 2
c) 3
d) 4
ANS:A
set-2 16) A function call can be a concurrent as well as a sequential statement.
a) True
b) False
ANS;A
set-3 17) Hold time is defined as the time required for the data to ________ after the triggering
edge of clock.
a. Increase
b. Decrease
c. Remain stable
d. All of the above
ANS:C
SET-1 21) It is possible to modify the STD_LOGIC_1164 package of IEEE library.
a) Trueb) False
ANS:B
set-2 19) A package may consist of _________ design units.
a) 2
b) 3
c) 4
d) 5
ANS:A
set-3 20) If a user wants to include his/her own package in the body, which library he/she must
use?
a) STD
b) IEEE
c) WORK
d) STD_LOGIC
ANS:C
23) Procedures are useful when _________
a) Functions are not synthesizable
b) Signals are needed to be declare
c) Multiple values are needed as a resultd) Architecture can’t contain some statement
ANS:C
2 set-1 24) Which of the following is the correct syntax to declare a package?
a)
PACKAGE package_name IS
declarations;
END package_name;
PACKAGE BODY package_name IS
Functions and procedures descriptions;
END package_name;
b)
PACKAGE package_name IS
declarations;
PACKAGE BODY package_body_name IS
Functions and procedures descriptions;
END package_name;
c)
PACKAGE package_name IS
declarations;
END package_name;
PACKAGE BODY package_body_name IS
Functions and procedures descriptions;
END package_name;
d) PACKAGE package_name IS
declarations;
PACKAGE BODY package_name IS
Functions and procedures descriptions;
END package_name;
ans:a
2 set-2 25) How to use a package in a VHDL design unit?
a)
USE PACKAGE package_name.part;
b)
LIBRARY library_name;
USE package_name.part;
c)
LIBRARY library_name;
USE library_name.package_name.part;
d)
USE library_name.package_name;
ANS:C
2 set-3 28) The code given below is a VHDL implementation of _________ARCHITECTURE my_circuit OF my_logic IS
BEGIN
WITH ab SELECT
y <= x0 WHEN “00”;
x1 WHEN “01”;
x2 WHEN “10”;
x3 WHEN “11”;
END my_circuit;
a) 4 to 1 MUX
b) 1 to 4 DEMUX
c) 8 to 1 MUX
d) 1 to 8 DEMUX
ANS:A
2 set-1 22) What should be the mode of signal a in the following function definition?
FUNCTION my_func (SIGNAL a : STD_LOGIC_VECTOR) RETURN INTEGER IS
…..;
a) IN
b) OUT
c) INOUT
d) BUFFER
ANS:A
2 set-2 30) Which of the following logic describes the EXOR gate?
a) y <= ((not a) OR (not b)) AND ((not a) OR (not b));b) y <= ((not a) OR b) AND (a OR (not b))
c) y <= ((not a) AND (not b)) OR ((not a) AND (not b));
d) y <= ((not a) AND b) OR (a AND (not b));
ANS:D
2 set-3 31)If T is an object, then T’LEFT attribute returns ________
a) Upper bound of object
b) Leftmost value of object
c) Leftmost value of an array
d) Lower bound of the object
ANS:B
2 set-1 26) 6. Among the four packages given below, which is the most used package of VHDL?
a) STD_LOGIC_1164
b) TEXTIO
c) STD_LOGIC_ARITH
d) NUMERIC_STD
ANS:A
2 set-2 27) Which of the following is true about both functions and procedures?
a) WAIT statement can’t be used
b) When declared in a package, both require package body
c) SIGNALs can’t be declared
d) RETURN is used in both
ANS:B
2 set-3 29) Output values of mealy type FSM are determined by its ________
a) Input values
b) Output values
c) Both input values and current state
d) Current state
ANS:C
2 set-1 32) What will be the value of x and y in the code given below?
TYPE bit_range IS ARRAY (0 TO 15) OF BIT;
VARIABLE x, y : INTEGER;
x := bit_range’RIGHT;
y := bit_range’LOW;
…
a) 0, 0
b) 0, 15
c) 15, 0
d) 15, 15
ans:c
2 set-2 33) Which kind of modeling is used in the following description?
ARCHITECTURE my_arch OF my_design IS
BEGIN
c<= a OR b;END my_arch;
a) Behavioral
b) Data flow
c) Structural
d) Behavioral and Dataflow
ANS:B
solution on clock skew problem
A. reduce connecting wire
B. H tree diagram
C. M tree diagram
D. none of above
ANSWER:B
one power optimization technique
A. using binary encoding in fsm
B. reduce power supply
C. reduce glitches in digital design
D. reduce connecting wire
ANSWER:C
floorplanning meansA. arrange blocks on chip
B. connect two block
C. calculate power dissipation
D. none of above
ANSWER:A
WHICH of the following statement is correct
A. Gate array based ASIC design by hand
B. semi custom asic design by hand
C. FPGA is programmed ASIC
D. Mix signal ASIC content only digital circuit
ANSWER:C
placement objective in chip design
A. Minimize cross talk between signals
B. increasing connecting wires
C. increases complexity in connecting wires
D. none of above
ANSWER:A
global routing means
A. minimize total interconnect length
B. maximize total interconnect length
C. maximize critical path delay
D. none of above
ANSWER:A
WHICH statement is incorrect
A. signal integrity due to substrate noise
B. EMI reduce by differential clocking system
C. EMI reduce by spread spectrum clockingD. global routing is not important in chip design
ANSWER:D
signal integrity means
A. poor clock signal routing
B. poor power arrangement
C. Inductive crosstalk
D. All of above
ANSWER:D
WHICH STATEMENT is correct
A. parasitic induced delays
B. signal integrity means clock skew
C. pads are not used in chip design
D. SRC AND DRC not important in chip design
ANSWER:A
SET-2
Before the commencement of design, the clocking strategy determine/s __________
a. Number of clock signals necessary for routing throughout the chip
b. Number of transistors used per storage requirement
c. Power dissipated by chip & the size of chip
d. All of the above
ANSWER: All of the above
Increase in the physical distance of H-tree _________the skew rate.
a. Increases
b. Stabilizes
c. Decreases
d. All of the above
ANSWER: Increases
Which among the following is/are identical in Mealy & Moore machines?
a. Combinational output signal
b. Clocked Process
c. Both a and b
d. None of the above
ANSWER: Clocked Process
In floorplanning, placement and routing are __________ tools.
a. Front end
b. Back end
c. Both a and b
d. None of the above
ANSWER: Back end
In floorplanning, which phase/s play/s a crucial role in minimizing the ASIC area and the
interconnection density?a. Placement
b. Global Routing
c. Detailed Routing
d. All of the above
ANSWER: Placement
In Gray coding, when the state machine changes state, ______ bit/s in the state vector changes the
value.
a. one
b. two
c. four
d. eight
ANSWER: one
Output values of Moore type FSM are determined by its ________
a) Input values
b) Output values
c) Clock input
d) Current state
ANS:D
In FSM diagram what does circle represent?
a) Change of state
b) State
c) Output value
d) Initial state
ANS:B
The time required for an input data to settle _____ the triggering edge of clock is known as 'Setup
Time'.
a. Before
b. During
c. After
d. All of the above
ANS:A
24) Before the commencement of design, the clocking strategy determine/s __________
a. Number of clock signals necessary for routing throughout the chip
b. Number of transistors used per storage requirement
c. Power dissipated by chip & the size of chip
d. All of the above
ANSWER: All of the above
25) Which method/s of physical clocking is/are a /the recursive structure where the memory
elements are grouped together to make the use of nearby or same distribution points?
a. H tree
b. Balanced tree clock network
c. Both a and b
d. None of the above
ANSWER: H tree
Which among the following is/are identical in Mealy & Moore machines?
a. Combinational output signal
b. Clocked Process
c. Both a and b
d. None of the above
ANSWER: Clocked Process
The full form of VLSI is ____________
a) Very Long Single Integration
b) Very Least Scale Integration
c) Very Large Scale Integration
d) Very Long Scale Integration
ANS:C
The devices which are based on fusible link or antifuse are _________time/s programmable.
a. one
b. two
c. four
d. infinite
ANSWER: one
60) In floorplanning, placement and routing are __________ tools.
a. Front end
b. Back end
c. Both a and bd. None of the above
ANSWER: Back end
61) In floorplanning, which phase/s play/s a crucial role in minimizing the ASIC area and the
interconnection density?
a. Placement
b. Global Routing
c. Detailed Routing
d. All of the above
ANSWER: Placement
WHICH of the following statement is correct
A. Gate array based ASIC design by hand
B. semi custom asic design by hand
C. FPGA is programmed ASIC
D. Mix signal ASIC content only digital circuit
ANSWER:C
SET-1 1) In Programmable Array Logic content
A. Programmable AND matrix and fix OR gate
B. Fix AND gate and programmable OR gate
C. AND matrix and OR matrix both programmabe
D. none of above
ANSWER:A
SET-2 2) CPLD means
A. Critical Program Logic Device
B. Complex Programmable Logic DeviceC. Cell based Programmable Logic Device
D. Complex Programmable Layout Device
ANSWER:B
SET-1 4) How much mux content in 3 input variable LUT
A. 8
B. 11
C. 10
D. 7
ANSWER:D
SET-2 20) Which statement is incorrect
a) SRAM cells are volatile
b) VHDL is hardware description language
c) CPLD content LUT
d) FPGA content sophisticated clock management
ANS:C
SET-3 6) How much bit content in 4 input variable LUT
A. 16
B. 3
C. 15
D. 14
ANSWER:A
SET-1 7) How much mux content in 2 input variable LUT
A. 8
B. 3
C. 4
D. 7ANSWER:B
SET-2 8) The complex programmable logic device content several PLD blocks and
A. A global interconnect matrix
B. field programmable switches
C. AND/OR array
D. a language compiler
ANSWER:A
SET-3 9) PLA, CPLD and FPGAs are all which type of devices
A. SLD
B. PLD
C. EPROM
D. SRAM
ANSWER:B
SET-1 10) Select wrong statement
A. CPLD consumes more power
B. FPGA consumes less power
C. CPLD content AND matrix
D. Very less registers content in FPGA
ANSWER:D
SET-2
SET-2 11) CLB means
A. Configurable Logic Block
B. Complex Logic Block
C. Current Logic BlockD. Common Logic Block
ANSWER:A
SET-3 12) The difference between a PAL & a PLA is ____________
a) PALs and PLAs are the same thing
b) The PLA has a programmable OR plane and a programmable AND plane, while the PAL only has a
programmable AND plane
c) The PAL has a programmable OR plane and a programmable AND plane, while the PLA only has a
programmable AND plane
d) The PAL has more possible product terms than the PLA
ANS:B
SET-1 13) If a PAL has been programmed once ____________
a) Its logic capacity is lost
b) Its outputs are only active HIGH
c) Its outputs are only active LOW
d) It cannot be reprogrammed
ANS:D
SET-2 14) The FPGA refers to ____________
a) First programmable Gate Array
b) Field Programmable Gate Array
c) First Program Gate Array
d) Field Program Gate Array
ANS:B
SET-3 15) The inputs in the PLD is given through ____________
a) NAND gates
b) OR gates
c) NOR gatesd) AND gates
ANS:D
SET-1 16) The cells in a FPGA may contain registers, look-up tables and memory
A) True
B) False
ANS: A
SET-2 17) The full form of VLSI is ____________
a) Very Long Single Integration
b) Very Least Scale Integration
c) Very Large Scale Integration
d) Very Long Scale Integration
ANS:C
SET-3 18) In FPGA, vertical and horizontal directions are separated by ____________
a) A line
b) A channel
c) A strobe
d) A flip-flop
ANS:B
2 SET-1 19) Which statement is correct
a) CPLD consumes more power
b) FPGA consumes more power
c) More flip flops in CPLD
d) FPGA content AND matrix
ans:A
2 SET-2 5) How much mux content in 4 input variable LUT
A. 16
B. 3
C. 15
D. 14
ANSWER:c
SET-3
2 SET-3 21) 3 input variable LUT content
a) 8 bit ram memory
b) 3 bit ram memory
c) 16 bit ram memory
d) 15 bit ram memory
ANS:A
2 SET-1 22) Many companies are transitioning to using FPGAs for their processor designs instead of
ASICs.
a) FPGA always outperform an ASIC
b) The development cycle for FPGA is much shorter
c) FPGAs are more space-efficient
d) FPGAa are both smaller and faster
ANS: B
2 SET-2 23) Most FPGA logic modules utilize a(n)____________approach to create the desired logic
functions.a) AND array
b) Look-up table
c) OR array
d) AND and OR array
ans:b
2 SET-3 24) Which gates are used on the output side as buffers in order to provide a programmable
output polarity in PAL 16 P8 devices?
a. AND
b. OR
c. EX-OR
d. NAND
ANS:C
The devices which are based on fusible link or antifuse are _________time/s programmable.
a. one
b. two
c. four
d. infinite
ANSWER: one
57) Which among the following is/are not suitable for in-system programming?
a. EPROM
b. EEPROM
c. Flashd. All of the above
ANSWER: EPROM
58) Simple Programmable Logic Devices (SPLDs) are also regarded as _____________.
a. Programmable Array Logic (PAL)
b. Generic Array Logic (GAL)
c. Programmable Logic Array (PLA)
d. All of the above
ANSWER: All of the above
which statement is correct
A. LUT content in CPLD
B. LUT content in FPGA
C. FPGA is not programmable
D. no of flip flop is more in CPLD compare FPGA
ANSWER:B
which following company design PROASIC3 FPGA
A. Cypress
B. Actel
C. Philips
D. Xilinx
ANSWER:B
SET-1 1) In Programmable Array Logic content
A. Programmable AND matrix and fix OR gate B. Fix AND gate and programmable OR gate
C. AND matrix and OR matrix both programmabe
D. none of above
ANSWER:A
SET-2 2) CPLD means
A. Critical Program Logic Device
B. Complex Programmable Logic Device
C. Cell based Programmable Logic Device
D. Complex Programmable Layout Device
ANSWER:B
SET-3 3) which statement is correct
A. LUT content in CPLD
B. LUT content in FPGA
C. FPGA is not programmable
D. no of flip flop is more in CPLD compare FPGA
ANSWER:B
SET-1 4) How much mux content in 3 input variable LUT
A. 8
B. 11
C. 10
D. 7
ANSWER:D
SET-2 20) Which statement is incorrect
a) SRAM cells are volatile
b) VHDL is hardware description language
c) CPLD content LUT
d) FPGA content sophisticated clock management
ANS:C
SET-3 6) How much bit content in 4 input variable LUT
A. 16
B. 3
C. 15
D. 14
ANSWER:A
SET-1 7) How much mux content in 2 input variable LUT
A. 8
B. 3
C. 4
D. 7
ANSWER:B
SET-2 8) The complex programmable logic device content several PLD blocks and
A. A global interconnect matrix
B. field programmable switches
C. AND/OR array
D. a language compiler
ANSWER:A
SET-3 9) PLA, CPLD and FPGAs are all which type of devices
A. SLD
B. PLD
C. EPROM
D. SRAM
ANSWER:B
SET-1 10) Select wrong statementA. CPLD consumes more power
B. FPGA consumes less power
C. CPLD content AND matrix
D. Very less registers content in FPGA
ANSWER:D
SET-2 11) CLB means
A. Configurable Logic Block
B. Complex Logic Block
C. Current Logic Block
D. Common Logic Block
ANSWER:A
SET-3 12) The difference between a PAL & a PLA is ____________
a) PALs and PLAs are the same thing
b) The PLA has a programmable OR plane and a programmable AND plane, while the PAL only has a
programmable AND plane
c) The PAL has a programmable OR plane and a programmable AND plane, while the PLA only has a
programmable AND plane
d) The PAL has more possible product terms than the PLA
ANS:B
SET-1 13) If a PAL has been programmed once ____________
a) Its logic capacity is lost
b) Its outputs are only active HIGH
c) Its outputs are only active LOW
d) It cannot be reprogrammed
ANS:D
SET-2 14) The FPGA refers to ____________
a) First programmable Gate Arrayb) Field Programmable Gate Array
c) First Program Gate Array
d) Field Program Gate Array
ANS:B
SET-3 15) The inputs in the PLD is given through ____________
a) NAND gates
b) OR gates
c) NOR gates
d) AND gates
ANS:D
SET-1 16) The cells in a FPGA may contain registers, look-up tables and memory
A) True
B) False
ANS: A
SET-2 17) The full form of VLSI is ____________
a) Very Long Single Integration
b) Very Least Scale Integration
c) Very Large Scale Integration
d) Very Long Scale Integration
ANS:C
SET-3 18) In FPGA, vertical and horizontal directions are separated by ____________
a) A line
b) A channel
c) A strobed) A flip-flop
ANS:B
2 SET-1 19) Which statement is correct
a) CPLD consumes more power
b) FPGA consumes more power
c) More flip flops in CPLD
d) FPGA content AND matrix
ans:A
2 SET-2 5) How much mux content in 4 input variable LUT
A. 16
B. 3
C. 15
D. 14
ANSWER:c
2 SET-3 21) 3 input variable LUT content
a) 8 bit ram memory
b) 3 bit ram memory
c) 16 bit ram memory
d) 15 bit ram memory
ANS:A
2 SET-1 22) Many companies are transitioning to using FPGAs for their processor designs instead of
ASICs.a) FPGA always outperform an ASIC
b) The development cycle for FPGA is much shorter
c) FPGAs are more space-efficient
d) FPGAa are both smaller and faster
ANS: B
23) Most FPGA logic modules utilize a(n)____________approach to create the desired logic
functions.
a) AND array
b) Look-up table
c) OR array
d) AND and OR array
ans:b
24) Which gates are used on the output side as buffers in order to provide a programmable
output polarity in PAL 16 P8 devices?
a. AND
b. OR
c. EX-OR
d. NAND
ANS:C
25) _________ is the fundamental architecture block or element of a target PLD.
a. System Partitioning
b. Pre-layout Simulation
c. Logic cell
d. Post-layout Simulation
ANS:
