VLSI Design and Technology MCQ with Aswers [181-200].

 VLSI Design and Technology MCQ with Answers [184-200].

181. Which process produces a circuit which is less prone to latch-up effect?

A) BiCMOS
B) cMOS
C) nMOS
D) pMOS

... Answer is A)
Explanation: BiCMOS process produces circuits that are less likely to suffer from latch-up problems where as CMOS circuits are very highly prone to latch-up problems.

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182. The parasitic PNP transistor has the effect of ........ carrier lifetime.

A) decreasing
B) increasing
C) exponentially decreasing
D) exponentially increasing

... Answer is A)
Explanation: The parasitic PNP transistor has the effect of reducing carrier lifetime in the n-base region.

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183. In two-stage op-amp, what is the purpose of compensation circuitry?

A) To provide high gain
B) To achieve stable closed-loop performance
C) To lower output resistance & maintain large signal swing
D) To establish proper operating point for each transistor in its quiescent state

... Answer is B)
The purpose of compensation circuitry is to achieve stable closed loop perforance.

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184. PSSR can be defined as the product of the ratio of change in supply voltage to change in output voltage of op-amp caused by the change in power supply & ...... of op-amp.

A) Open-loop gain
B) Closed-loop gain
C) Both A & N
D) None of the above

... Answer is A)
No Explanation.

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185.The reduction in carrier lifetime brings about .............

A) reduction in current
B) reduction in voltage
C) reduction in alpha
D) reduction in beta

... Answer is D)
Explanation: The parasitic PNP transistor has the effect of reducing carrier lifetime in the n-base region which results in radiation in beta.

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186. Latch-up is brought about by BJTs ...........

A) With positive feedback
B) with negetive feedback
C) no feedback
D) Withought BJT

... Answer is A)
Explanation: Latch-up occurs due to BJTs for silicon-controlled rectifiers with positive feedback and virtually short circuit the power and ground rail.

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187. According to the principle of current mirror, if gate-source potentials of two identical MOS transistors are equal, then the channel currents should be .........

A) Different
B) Equal
C) Both A & B
D) None of the above

... Answer is B)
No Explanation.

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188. Due to the limitations of the testers, the functional test is usually performed at speed ..... the target speed.

A) Lower than
B) Equal to
C) Greater than
D) None of the above

... Answer is A)
Due to the limitations of the testers, the functional test is usually performed at speed lower than the target speed.

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189. High observability indicates that ....... number of cycles are required to measure the output node value.

A) Less
B) Equal
C) More
D) None of the above

... Answer is A)
High observability indicates that less number of cycles are required to measure the output node value.

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190. Latch-up is the generation of ..........

A) low resistance path
B) high resistance path
C) low impedance path
D) High impedance path

... Answer is C)
Explanation: Latch-up is the generation of low-impedance path in CMOS chips between the power supply and ground rails.

191. In two-stage op-amp, what is the purpose of compensation circuitry?

A) To establish proper operating point for each transistor in its quiescent state
B) To lower output resistance & maintain large signal swing
C) To achieve stable closed-loop performance
D) To provide high gain

... Answer is C)
The purpose of compensation circuitry is to achieve stable closed-loop performance.

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192. BJT gain should be ......... to avoid latch-up effect.

A) Less
B) Equal
C) More
D) None of the above

... Answer is A)
BJT gain should be less to avoid latch-up effect.

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193. The transistors used in BiCMOS are .........

A) MOSFET
B) BJT
C) JFET
D) Both MOSFET and BJT

... Answer is D)
Explanation: BiCMOS is a combination of both MOSFET and BJT.

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194. In BiCMOS inverter, the BJT used are ......

A) Only Pnp BJT
B) Only npn BJT
C) Both npn and pnp BJT
D) Multi emitter npn BJT

... Answer is B)
Explanation: npn BJTs are used in BiCMOS inverter.

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195. Basically, an observability of an internal circuit node is a degree to which one can observe that node at the ........... of an integrated circuit.

A) Inputs
B) Outputs
C) Both A & B
D) None of the above

... Answer is B)
No Explanation.

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196. Which method is used to determine structural defects?

A) algorithmic test pattern
B) deterministic test pattern
C) random test pattern
D) exhaustic test pattern

... Answer is B)
Explanation: Deterministic test patterns are used to detect specific faults or structural faults for a circuit under test.

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197. Exhaustive test pattern determines ........

A) logic level faults
B) gate level faults
C) functional faults
D) Structural faults

... Answer is B)
Explanation: Exhaustive test pattern method detects all gate level struck-at fault and also bridging fault.

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198. Which is not suitable for circuits having large N values?

A) pseudo-exhaustive test pattern method
B) exhaustive test pattern method
C) random test pattern method
D) Exhaustic test pattern method

... Answer is D)
Explanation: Exhaustive test pattern method is not suitable for circuit having large N values since there is a limit for fault coverage.

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199. In which method sequences are repeatable?

A) pseudo-exhaustive test pattern method
B) exhaustive test pattern method
C) pseudo-random test pattern method
D) random test pattern method

... Answer is C)
Explanation: Pseudo-random test pattern method have properties similar to random pattern sequence but the sequence are repeatable.

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200. Which method needs fault simulation?

A) pseudo-exhaustive test pattern method
B) exhaustive test pattern method
C) deterministic test pattern method
D) random test pattern method

... Answer is B)
Explanation: Exhaustive test pattern method needs fault simulation for determining fault coverage where as pseudo-exhaustive test pattern method does not need fault simulation.

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