VLSI Design and Technology MCQ [20-40] with Answer.

 VLSI Design and Technology MCQ with Answers [21-40].

21. In two-stage op-amp, what is the purpose of compensation circuitry?

A) To establish proper operating point for each transistor in its quiescent state
B) To lower output resistance & maintain large signal swing
C) To achieve stable closed-loop performance
D) To provide high gain

... Answer is C)
The purpose of compensation circuitry is to achieve stable closed-loop performance.

---

22. impurities are added to the wafer of the crystal.

A) P impurities
B) N impurities
C) Crystal
D) Silicon

... Answer is A)
Explanation: p impurities are introduced as the crystal is grown. This increases the hole concentration in the device.

---

23. In nMOS device, gate material could be.......

A) polysilicon
B) Boron
C) Phosphorous
D) Silicon

... Answer is A)
Explanation: In nMOS device, the gate material could be metal or polysilicon. This polysilicon layer has heavily doped polysilicon deposited by CVD.

---

24. In CMOS circuits, which type of power dissipation occurs due to switching of transient current and charging & discharging of load capacitance?

A) Dynamic dissipation
B) Static dissipation
C) Both A & B
D) None of the above

... Answer is A)
No Explanation.

---

25. In accordance to the scaling technology, the total delay of the logic circuit depends on

A) The voltage through which capacitance must be charged
B) The capacitor to be charged
C) Available current
D) All of the above

... Answer is D)
All of the above

---

26. The photoresist layer is exposed to .......

A) Ultraviolet light
B) Visible light
C) Infra red light
D) LED

... Answer is A)
Explanation: The photoresist layer is exposed to ultraviolet light to mark the regions where diffusion is to take place.

---

27. In a chip, which type/s of pad design/s is/are adopted to solve the problem of pin count?

A) Output pad design
B) input pad design
C) Three state pad design
D) All of the above

... Answer is C)
Three state pad design

---

28. Which level of routing resources are supposed to be the dedicated lines allowing output of each tile to connect directly to every input of eight surrounding tiles?

A) High speed, very long-line resources
B) Efficient long-line resources
C) High performance global networks
D) Ultra-fast local resources

... Answer is D)
Ultra fast local resources

---

29. The power consumption of static CMOS gates varies with the ....... of power supply voltage.

A) Cube
B) Square
C) Fourth power
D) 1/8 th power

... Answer is B)
Square

---

30. What kind of substrate is provided above the barrier to dopants?

A) conducting
B) semiconducting
C) insulating
D) Silicon

... Answer is C)
Explanation: Above a layer of silicon dioxide which acts as a barrier, an insulating layer is provided upon which other layers may be deposited and patterned.

31. Which factor/s play/s a crucial role in determining the speed of CMOS logic gate?

A) Gain factor of MOS
B) Load Capacitance
C) Supply voltage
D) All of the above

... Answer is D)
All of the above

---

32. In high noise margin (NMH), the difference in magnitude between the maximum HIGH output voltage of driving gate and the maximum HIGH voltage is recognized by the ....... gate.

A)Receiving
B) Driven
C) Both A & B
D) None of the above

... Answer is A)
Receiving

---

33. Maze routing is used to determine the ........ path for a single wire between a set of points, if any path exists.

A) Shortest
B) Average
C) longest
D) None of the above

... Answer is A)
Maze routing is used to determine the shortest path for a single wire between a set of points, if any path exists.

---

34. Heavily doped polysilicon is deposited using ........

A) chemical vapour deposition
B) chemical vapour decomposition
C) dry deposition
D) Chemical deposition

... Answer is B)
Explanation: The polysilicon layer consists of heavily doped polysilicon deposited by chemical vapour deposition.

---

35. Contact cuts are made in .......

A) diffusion layer
B) Source
C) Drain
D) Metal layer

... Answer is B)
Explanation: Contact cuts are made in the desired polysilicon area, source and gate. COntact cuts are those places where connection has to be made.

---

36. In diffusion process ...... impurity is desired.

A) n type
B) p type
C) np type
D) None of the above

... Answer is A)
Explanation: Diffusion is carried out by heating the wafer to high temperature and passing a gas containing the desired ntype impurity.

---

37. In spartan-3 family architecture, which programmable functional element accepts two 18 bit binary numbers as inputs and computes the product?

A) Input output Block
B) Configurable Logic Blocks
C) Multiplier Blocks
D) Block Ram

... Answer is C)
Multiplier Blocks

---

38. Which type of CPLD packaging comprises pins on all four sides that wrap around the edges of chip?

A) Ceramic Pin Grid Array (PGA)
B) Plastic-Leaded Chip Carrier (PLCC)
C) Ball Grid Array (BGA)
D) Quad Flat Pack (QFP)

... Answer is B)
Plastic - Leaded cheap carrier

---

39. Which is used for the interconnection?

A) Alluminium
B) Boron
C) Oxygen
D) Silicon

... Answer is A)
Explanation: Aluminium is the suitable material used for the circuit interconnection or connecting two layers.

---

40. An antifuse element initial provides ....... between two conductors in absence of the application of sufficient programming voltage.

A) Conduction
B) Insulation
C) Both A & B
D) None of the above

... Answer is B)
Insulation

Next Page : 1   2   3   4   5   6   7   8   9   10