VLSI Design and Technology MCQ with Answers [121 - 140].

1. Fast gate can be built by keeping ........

A) low output capacitance
B) high output capacitance
C) high on resistance
D) None of the above

... Answer is A)
Explanation: Fast gate can be built by keeping the output capacitance small and by decreasing the on resistance of the transistor.

---

2. The transconductance of a bipolar is given by ............

A) Ic/(kT/q)
B) (q/KT)/Ic
C) (kT/q)/Ic
D) Ic/(q/KT)

... Answer is A)
Explanation: Transconductance gm of a bipolar transistor is given by gm = Ic/(kT/q). Transconductance is the electrical characteristic relating the current through the output of a device to the voltage across the input of a device.

---

3.In floorplanning, placement and routing are ............ tools.

A) Back end
B) Front End
C) Both A & B
D) None of the above

... Answer is A)
In floorplanning, placement and routing are back end tools.

---

4. In CMOS inverter, the propagation delay of a gate is the/an .......... transition delay time for the signal during propagation from input to output especially when the signal changes its value.

A) Lowest
B) Average
C) Highest
D) None of the above

... Answer is B)
In CMOS inverter, the propagation delay of a gate is the/an average transition delay time for the signal during propagation from input to output especially when the signal changes its value.

---

5.In floorplanning, which phase plays a crucial role in minimizing the ASIC area and the interconnection density?

A) Global Routing
B) Detailed Routing
C) Placement
D) None of the above

... Answer is C)
In floorplanning, placement phase plays a crucial role in minimizing the ASIC area and the interconnection density.

---

6. In MOS devices, the current at any instant of time is ......... of the voltage across their terminals.

A) constant & independent
B) constant & dependent
C) Variable & independent
D) Variable & dependent

... Answer is A)
In MOS devices, the current at any instant of time is constant and independent of the voltage across their terminals.

---

7.An ideal op-amp has .......

A) Infinite differential voltage gain
B) Infinite input resistance
C) Zero output resistance
D) All of the above

... Answer is D)
No explanation

---

8. Which attribute in synthesis process specify/ies the resistance by controlling the quantity of current it can source?

A) Drive attribute
B) Load attribute
C) Arrival time attribute
D) None of the above

... Answer is A)
No explanation.

---

9. Register transfer level description specifies all of the registers in a design & ......... logic between them.

A) Combinational
B) Sequential
C) Both A & B
D) None of the above

... Answer is A)
No Explanation

---

10. Which among the following is an output generated by synthesis process?

A) RTL VHDL description
B) Attributes & Library
C) Circuit constraints
D) Gate-level net list

... Answer is D)
No Explanation

31. gm is ........ on input voltage Vbe.

A) inversely proportional
B) Proportional
C) not dependent
D) Exponentially dependent

... Answer is D)
Explanation: Transconductance gm is exponentially dependent on input voltage Vbe (base to emitter voltage).

---

32. Transconductance is a ..........

A)strong function
B) weak function
C) strong and weak function
D) None of the above

... Answer is B)
Explanation: Transconductance gm is a weak function of transistor size.

---

33. Stuck open (off) fault occur/s due to ........

A) Large separation of drain or source diffusion from the gate
B) An incomplete contact (open) of source to drain node
C) Both A & B
D) None of the above

... Answer is C)
No explanation.

---

34. In pull-up network, PMOS transistors of CMOS are connected in parallel with the provision of conducting path between output node & Vdd yielding .......... output.

A) Zero
B) One
C) Two
D) Three

... Answer is B)
In pull-up network, PMOS transistors of CMOS are connected in parallel with the provision of conducting path between output node & Vdd yielding one output.

---

35. Which among the following is not a characteristic of 'Event-driven Simulator'?

A) Storage of state values & time information
B) Identification of timing violations
C) No event scheduling
D) Time delay calculation

... Answer is C)
No Explanation

---

36. Which of the following is true when inputs are controlled by equal amounts of charge?

A) Cg(MOS) greater than Cbase(bipolar)
B) Cg(MOS) = Cbase(bipolar)
C) Cg(MOS) lesser than Cbase(bipolar)
D) None of the above

... Answer is B)
Explanation: Cg(MOS) = Cbase(bipolar) when inputs are controlled by equal amounts of charge, and then gm(bipolar) >> gm(MOS).

---

37. In bipolar transistor, which is heavily doped?

A) Emitter region
B) Base region
C) Collector region
D) base and emitter

... Answer is A)
Explanation: In bipolar transistor, emitter region is heavily doped and the base region is lightly doped.

---

38. Bipolar transistor exhibits ....... delay.

A) turn off
B) turn on
C) Storage
D) All of the above

... Answer is D)
Explanation: Bipolar transistors exhibits turn-on, turn-off, storage delays.

---

39. Which has better I/A?

A) bipolar
B) nMOS
C) pMOS
D) CMOS

... Answer is D)
Explanation: Current/Area (I/A) of bipolar is five times better than CMOS and this can be calculated using base resistance and base transit time.

---

40. Why is multiple stuck-at fault model preferred for DUT?

A) Because single stuck-at tests cover major % of multiple stuck-at faults & unmodeled physical defects
B) Because single stuck-at fault model is independent of design style & technology
C) Because complexity of test generation is reduced to greater extent in multiple stuck-at fault models
D) all of the above

... Answer is D)
No Explanation.

Next Page : 1    2     3     4     5    6    7     8     9     10