VLSI Design and Technology MCQ with Answers [141-160].

1. Which among the following EDA tool is available for design simulation?

A) ALDEC
B) OrCAD
C) VIVElogic
D) Simucad

... Answer is C)
No Explanation

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2. The BiCMOS are preferred over CMOS due to ........

A) Sensitivity is less with respect to the load capacitance
B)Switching speed is more compared to CMOS
C) High current drive capability
D) All of the above

... Answer is D)
No Explanation.

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3. The high current driving capability of the BiCMOS is due to .........

A) PMOS in saturation mode
B) NMOS in saturation mode
C) CMOS
D) BJT

... Answer is D)
Explanation: BJT has the high current driving capability.

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4. The transistors used in BiCMOS are ........

A) MOSFET
B) BJT
C) Both MOSFET and BJT
D) JFET

... Answer is C)
Explanation: BiCMOS is a combination of both MOSFET and BJT.

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5. Which among the following functions are performed by MSI category of IC technology?

A) Microprocessor/A/D
B) Gates, Op-amps
C) Memory/DSP
D) Filters

... Answer is D)
MSI category of IC technology perform filter functions.

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6. An Assert is ....... command.

A) Concurrent
B) Sequential
C) Both A & B
D) None of the above

... Answer is C)
An assert is concurrent and sequential command.

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7. Timing analysis is more efficient with synchronous systems whose maximum operating frequency is evaluated by the .......... path delay between consecutive flip-flops.

A) Shortest
B) Average
C) Longest
D) None of the above

... Answer is C)
Timing analysis is more efficient with synchronous systems whose maximum operating frequency is evaluated by the longest path delay between consecutive flip-flops.

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8. The high current driving capability of the BiCMOS is due to ........

A) PMOS in saturation mode
B) NMOS in saturation mode
C) CMOS
D) BJT

... Answer is D)
Explanation: BJT has the high current driving capability.

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9. Which of the following is the drawback of the BiCMOS circuits?

A) Bipolar transistors are used for driving current to the load capacitance but not for the logic operations
B) Sensitivity is less load capacitance
C) Increased fabrication Complexity
D) None of the above

... Answer is C)
Explanation: The other 2 are the merits of BiCMOS, Increased fabrication Complexity is a demerit of BiCMOS circuits.

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10. In BiCMOS inverter, the BJT used are .......

A) Only Pnp BJT
B) Only nPn BJT
C) Both npn and pnp BJT
D) Multi emitter npn BJT

... Answer is B)
Explanation: npn BJTs are used in BiCMOS inverter.

31. The Bipolar Transistor is fabricated on .......

A) P-well in n Substrate
B) N-well in p Substrate
C) Same substrate of nMOS
D) Same substrate of pMOS

... Answer is C)
Explanation: BiCMOS is fabricated on the same substrate of nMOS.

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32. The n-well collector is formed by .......

A)Lightly doped n-type diffused layer on p-Substrate
B) Heavily doped n-type diffused layer on p-Substrate
C) Lightly doped n-type epitaxial layer on p-Substrate
D) Heavily doped n-type epitaxial layer on p-Substrate

... Answer is C)
Explanation: To make the doping concentration less than the emitter.

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33. Why is the use of mode buffer prohibited in the design process of synthesizer?

A) To prevent the occurrence of glitches & metastability
B) To avoid mixing of clock edges
C) Because Maximum ASIC vendors fail to support mode buffer in librari
D) Because critical path has preference in placement

... Answer is C)
No Explanation.

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34. If a port is declared as buffer, then which problem is generated in hierarchical design due to mapping with port of buffer mode of other entities only?

A) Functional Modeling
B) Behavioral Modeling
C) Structural Modeling
D) Data flow modeling

... Answer is C)
No Explanation.

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35. In BiCMOS, the analysis of the operation of BJT is well explained by .......

A) Emitter resister model
B) Ebers Moll Model
C) RC Model
D) Hybrid Model

... Answer is B)
No Explanation.

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36. What is the work of BJT in BiCMOS?.

A) Voltage controlled Current source
B) Voltage controlled voltage source
C) Current controlled current source
D) Current controlled voltage source

... Answer is A)
Explanation: The Current Ic and Ie are controlled by base emitter bias voltage.

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37. In Gray coding, when the state machine changes state, ______ bit/s in the state vector changes the value.

A) 1
B) 2
C) 4
D) 6

... Answer is A)
No Explanation

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38. Which UART component/s divide/s the system clock to provide the bit clock with the period equal to one bit time and Bclock x 8?

A) Transmitter Section
B) Receiver Section
C) Baud rate generator
D) None of the above

... Answer is C)
No Explanation

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39. What is/are the necessity/ies of Simulation Process in VHDL?

A) Reduction of development time
B) Requirement to test designs before implementation & usage
C) Decrease the time to market
D) All of the above

... Answer is D)
All of the above.

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40. Which type of simulation mode is used to check the timing performance of a design?

A) Transistor-level
B) Switch-level
C) Behavioural
D) Gate level

... Answer is D)
No Explanation

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