VLSI Design and Technology MCQ with Answers [101 - 120].

1. CMOS inverter has ..... regions of operation.

A) 3
B) 5
C) 7
D) 4

... Answer is B)
Explanation: CMOS inverter has five distinct regions of operation which can be determined by plotting CMOS inverter current versus Vin.

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2. In the region where inverter exhibits gain, the two transistors are in ....... region.

A)saturation
B) Non-saturation
C) Cutt off
D) Linear

... Answer is A)
Explanation: In the region where the inverter exhibits gain, the two transistors n and p operates in saturation region.

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3. The devices which are based on fusible link or antifuse are ........ time/s programmable.

A) 1
B) 2
C) 3
D) 4

... Answer is A)
The devices which are based on fusible link or antifuse are one time/s programmable.

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4. Which among the following is/are identical in Mealy & Moore machines?

A) Clocked Process
B) Combinational output signal
C) None of the above
D) Both A & B

... Answer is A)
Clocked process are identical in Mealy & Moore machines.

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5. In synthesis flow, which stage/s is/are responsible for converting an unoptimized boolean description to PLA format?

A) Optimization
B) Translation
C) Flattening
D) None of the above

... Answer is C)
No explanation

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6. If n-transistor conducts and has large voltage between source and drain, then it is said to be in ....... region.

A) saturation
B) Non saturation
C) None of the above
D) Both A & B

... Answer is A)
Explanation: If n-transistor conducts and has large voltage between source and drain, then it is in saturation.

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7. If p-transistor is conducting and has small voltage between source and drain, then it is said to work in .........

A) saturation region
B) Non saturation resistive region
C) linear region
D) Cutt off region

... Answer is B)
Explanation: If p-transistor is conducting and has small voltage between source and drain, then it is said to be in unsaturated resistive region.

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8. In synthesis flow, the flattening process generates a flat signal representation of _____levels. A. AND B. OR C. NOT D. EX-OR

A) A & B
B) A & C
C) C & D
D) B & D

... Answer is A)
No Explanation

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9. Which among the following constraint/s is/are involved in a state-machine description?

A) State transitions & output specifications
B) State variable & clock
C) Reset condition
D) All of the above

... Answer is D)
No Explanation

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10. Which method is adopted for acquiring spike-free outputs?

A)Mealy machine with clocked outputs
B) Moore machine with clocked outputs
C) Output state machine
D) All of the above

... Answer is D)
No Explanation.

31. Simple Programmable Logic Devices (SPLDs) are also regarded as ..........

A) Generic Array Logic (GAL)
B) Programmable Array Logic (PAL)
C) Programmable Logic Array (PLA)
D) All of the above

... Answer is D)
All of the above

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32. If both the transistors are in saturation, then they act as ........

A)voltage source
B) Divider
C) Buffer
D) Current source

... Answer is D)
Explanation: When both the transistors are in saturation, then act as current sources so that the equivalent circuit is two current sources between Vdd and Vss.

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33. In CMOS inverter, transistor is a switch having ......

A) finite off resistance
B) Infinite off resistance
C) infinite on resistance
D) Buffer

... Answer is B)
Explanation: In CMOS inverter, transistor is a switch having finite on resistance and infinite off resistance.

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34. If βn = βp, then Vin is equal to ..........

A) Vdd
B) Vss
C) 2Vdd
D)0.5 Vdd

... Answer is D)
Explanation: If βn = βp, then Vin = 0.5Vdd which implies that the changeover between logic levels is symmetrically disposed about the point.

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35. Hold time is defined as the time required for the data to ......... after the triggering edge of clock.

A) Increase
B) Decrease
C) Remain Stable
D) None of the above

... Answer is C)
Hold time is defined as the time required for the data to remain stable after the triggering edge of clock.

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36. The output of sequential circuit is regarded as a function of time sequence of .......... A. Inputs B. Outputs C. Internal States D. External States

A) B & D
B) A & C
C) A & D
D) None of the above

... Answer is B)
A & C

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37. Mobility depends on ........

A) Transverse electric field
B) channel length
C) Vg
D) Vdd

... Answer is A)
Explanation: Mobility is affected by the transverse electric field and thus also depends on Vgs and the mobility of p-device and n-device are inherently unequal.

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38. What is the input resistance of CMOS inverter?

A) Very low
B) Low
C) High
D) None of the above

... Answer is C)
Explanation: Input resistance of CMOS inverter is extremely high as it is a perfect insulator and draws no dc input source.

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39. CMOS inverter has ...... output impedance.

A) Low
B) High
C) Very high
D) None of the above

... Answer is A)
Explanation: CMOS inverter has low output impedance and this makes it less prone to noise and disturbance.

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40. Increasing fan-out ........ the propagation delay.

A) Increases
B) Decreases
C) Exponentially decreases
D) None of the above

... Answer is A)
Explanation: In CMOS inverter, increasing the fan-out also increases the propagation delay. Fan-out is a term that defines the maximum number of digital inputs that the output of a single logic gate can feed.

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