VLSI Design and Technology MCQ with Answer [41-60].

41. CMOS technology is used in developing which of the following?

A) digital logic circuits
B) Microprocessor
C) Microcontroller
D) All of the above

... Answer is D)
Explanation: CMOS technology is used in developing microcontrollers, microprocessors, digital logic circuits and other integrated circuits.

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42. Which type of MOSFET exhibits no current at zero gate voltage?

A) Enhancement MOSFET
B) Depletion MOSFET
C) Both A & B
D) None of the above

... Answer is A)
Enhancement MOSFET exhibits no current at zero gate voltage

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43. Before the commencement of design, the clocking strategy determine/s .......

A) Number of transistors used per storage requirement
B) Number of clock signals necessary for routing throughout the chip
C) Power dissipated by chip & the size of chip
D) All of the above

... Answer is D)
All of the above

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44. P-well is created on ......

A) n substrate
B) p substrate
C) n & p substrate
D) None of the above

... Answer is A)
p-well is created on n substrate

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45. CMOS has ..........

A) high power dissipation
B) high noise margin
C) high packing density
D) high complexity

... Answer is C)
Explanation: Some of the properties of CMOS are that it has low power dissipation, high packing density and low noise margin.

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46. Which among the following is an output generated by synthesis process?

A) RTL VHDL description
B) Atributes and library
C) Gate-level net list
D) Corcuit constraints

... Answer is C)
Gate level net list output generated by synthesis process

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47. Which among the following is not a characteristic of ‘Event-driven Simulator’?

A) Storage of state values & time information
B) Identification of timing violations
C) No event scheduling
D) Time delay calculation

... Answer is C)
No event scheduling is not a characteristic of ‘Event-driven Simulator’

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48. In synthesis process, the load attribute specify/ies the existing amount of .......... load on a particular output signal.

A) Capacitive
B) Resistive
C) Inductive
D) All of the above

... Answer is D)
All of the above

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49. Register transfer level description specifies all of the registers in a design & ....... logic between them.

A) Combinational
B) Sequential
C) Both A & B
D) None of the above

... Answer is A)
Combinational

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50. Oxidation process is carried out using ........

A) low purity oxygen
B) Hydrogen
C) Sulphur
D) Nitrogen

... Answer is B)
Oxidation process is carried out using hydrogen.

51. The output of sequential circuit is regarded as a function of time sequence of .......... A. Inputs B. Outputs C. Internal States D. External States

A) A & D
B) A & C
C) B & D
D) B & C

... Answer is B)
A & C

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52. Which type of digital systems exhibit the necessity for the existence of at least one feedback path from output to input?

A)Combinational System
B) Sequential System
C) Both A & B
D) None of the above

... Answer is B)
Sequential System

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53. In CMOS fabrication, the photoresist layer is exposed to ..........

A) ultraviolet light
B) Visible light
C) fluorescent
D) Infra red light

... Answer is A)
Explanation: The photoresist layer is exposed to ultraviolet light to mark the regions where diffusion is to take place.

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54. Photoresist layer is formed using ........

A) light sensitive polymer
B) High sensitive polymer
C) silicon di oxide
D) Polysilicon

... Answer is A)
Explanation: Light sensitive polymer is used to form the photoresist layer. Photoresist is a light sensitive material used to form patterned coating on a surface.

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55. Few parts of photoresist layer is removed by using .......

A) acidic solution
B) basic solution
C) Neutral solution
D) Diluted water

... Answer is A)
Explanation: Few parts of photoresist layer is removed by treating the wafer with basic or acidic solution. Acidic solutions are those which have pH less than 7 and basic solutions have greater than 7.

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56. The time required for an input data to settle ....... the triggering edge of clock is known as ‘Setup Time’.

A)Before
B) After
C) During
D) None of the above

... Answer is A)
No explanation

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57. Which attribute in synthesis process specify/ies the resistance by controlling the quantity of current it can source?

A) Arrival time attribute
B) Load attribute
C) Drive attribute
D) All of the above

... Answer is C)
Drive Attribute

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58. N-well is formed by .......

A) Decomposition
B) Defusion
C) Dispertion
D) Filtering

... Answer is B)
Explanation: N-well is formed by using ion implantation or diffusion. Ion implantation is a process by which ions of a material are accelerated in an electrical field and impacted into a solid. Diffusion is a process in which net movement of ions or molecules plays a major role.

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59. Which type of CMOS circuits are good and better?

A) p-well
B) n-well
C) All of the above
D) None of the above

... Answer is B)
Explanation: N-well CMOS circuits are better than p-well CMOS circuits because of lower substrate bias effect.

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60. P-well doping concentration and depth will affect the .......

A)Vss
B) Vdd
C) Vgs
D) Threshold voltage

... Answer is D)
Explanation: Diffusion should be carried out very carefully, as doping concentration and depth will affect both threshold voltage and breakdown voltage.

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