VLSI Design and Technology MCQ with Answer [161-180].

 VLSI Design & Technology MCQ with Answers [161-180].

161. In BiCMOS, MOS switches are used to ........

A) drive input loads
B) drive output loads
C) To amplify the input voltage
D) To perform logic functions

... Answer is D)
Explanation: In BiCMOS circuits, MOS switches are used to perform logic functions. The ability to turn the power MOS “ON” and “OFF” allows the device to be used as a very efficient switch with switching speeds much faster than standard bipolar junction transistors.

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162. An antifuse element initial provides ........ between two conductors in absence of the application of sufficient programming voltage.

A) Insulation
B) Conduction
C) Both A & B
D) None of the above

... Answer is A)
An antifuse element initial provides insulation between two conductors in absence of the application of sufficient programming voltage.

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163. Which type of CPLD packaging comprises pins on all four sides that wrap around the edges of chip?

A) Quad Flat Pack (QFP)
B) Plastic-Leaded Chip Carrier (PLCC)
C) Ball Grid Array (BGA)
D) Ceramic Pin Grid Array (PGA)

... Answer is B)
Plastic leaded chip carrier CPLD packaging comprises pins on all four sides that wrap around the edges of chip

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164. In BiCMOS, bipolar transistors are used to ..........

A) To perform logic functions
B) To amplify the input voltage
C) drive input loads
D) drive output loads

... Answer is D)
Explanation: In BiCMOS, bipolar transistors are used to drive output loads. Bipolar transistor can also be used as amplifier, switch or as an oscillator.

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165. The nMOS and pMOS transistors used in BiCMOS is ..........

A) only pMOS
B) only nMOS
C) Enhancement mode
D) Depletion mode

... Answer is C)
Explanation: The nMOS and pMOS transistors used in BiCMOS device operates in enhancement mode. Enhancement mode devices are mostly common switching elements in MOS.

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166. Which level of routing resources are supposed to be the dedicated lines allowing output of each tile to connect directly to every input of eight surrounding tiles?

A) Efficient long-line resources
B) Ultra-fast local resources
C) High performance global networks
D) High speed, very long-line resources

... Answer is B)
No Explanation

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167. Maze routing is also known as ...........

A)Lee/Moore algorithm
B) Prim’s algorithm
C) Viterbi’s algorithm
D) Quine-McCluskey algorithm

... Answer is A)
Maze routing is also known as lee/Moore algorithm.

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168. The inverter has ........

A) low input impedance
B) low output impedance
C) high input and output impedance
D) Low power dessipition

... Answer is B)
Explanation: The inverter has low output impedance and low input impedance. These are some of the properties of a BiCMOS inverter.

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169. The inverter has ..........

A) occupies smaller area
B) high current driving capability
C) High noise margin
D) All of the above

... Answer is D)
Explanation: The inverter has high current driving capability, occupies smaller area and has high noise margins.

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170. BiCMOS has ......... standby leakage current.

A) very low
B) Low
C) High
D) None of the above

... Answer is C)
Explanation: BiCMOS has higher standby leakage current and thus has high power consumption.

171.In a chip, which type/s of pad design/s is/are adopted to solve the problem of pin count?

A) Input pad design
B) Output pad design
C) Three state pad design
D) All of the above

... Answer is C)
No Explanation.

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172. In high noise margin (NMH), the difference in magnitude between the maximum HIGH output voltage of driving gate and the maximum HIGH voltage is recognized by the ......... gate.

A)Receiving
B) Driven
C) Both A & B
D) None of the above

... Answer is A)
Receiving

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173.Which factor/s play/s a crucial role in determining the speed of CMOS logic gate?

A) Supply voltage
B) Load Capacitance
C) Gain factor of MOS
D) All of the above

... Answer is D)
No Explanation.

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174. In spartan-3 family architecture, which programmable functional element accepts two 18 bit binary numbers as inputs and computes the product?

A) Input Output Blocks
B) Configurable Logic Blocks
C) Block RAM
D) Multiplier Blocks

... Answer is D)
None of the above.

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175. The MOSFETS are arranged in this configuration to provide ...........

A) Zero static power dissipation
B) Both zero static power dissipation and high input impedance
C) High input impedence
D) None of the above

... Answer is C)
Explanation: MOSFETs provide zero static power dissipation and high input impedance.

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176. The BJTs in the BICMOS circuit is in ........... configuration.

A)Totem pole
B) Push-Pull
C) Active high
D) Active low

... Answer is A)
Explanation: In BiCMOS circuit, the BJT transistors are in Totem pole configuration.

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177. For improved base current discharge ......... enhancement type nMOS devices have to be added.

A) One
B) Two
C) Three
D) Four

... Answer is B)
Explanation: For improved base current discharge, two enhancement type nMOS transistors have to be added.

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178. Latch-up can be induced by ........

A) Reflected radiation
B) Incedent radiation
C) diffracted radiation
D) Etching

... Answer is B)
Explanation: Latch-up can be induced by glitches on the supply rail or by incident radiation.

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179. In accordance to the scaling technology, the total delay of the logic circuit depends on .......

A) The voltage through which capacitance must be charged
B) The capacitor to be charged
C) Available current
D) All of the above

... Answer is D)
No Explanation.

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180. How many transistors might bring up latch up effect in p-well structure?

A) 1
B) 2
C) 3
D) 4

... Answer is B)
Explanation: Two transistors and two resistances might bring up the latch-up effect in p-well structure. These are associated with p-well and with regions of the substrate.

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